Modelling and Synthesis of Printed Circuit Boards Testing Systems based on Timed Hard Petri Nets

Abstract

This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used, which allow conflicts identification and exclusion related to both the processes time synchronization and processes timing constraints. The developed TSPN model of the delay time evaluation system comprises the test signal generator and the time delay analyzer. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). THPN consists of processing elements and logical connections between them. For each processing element analytical model and AHDL code were developed. The implementation of the delay time evaluation system was done by direct mapping of the THPN into the Field-Programmable Gate Array (FPGA) circuits. FPGA architectures present advantages such as high parallelism, control processing speed-up and reconfigurability option. The direct mapping method has a linear algorithmic complexity and is not affected by state explosion problem. The transparent correspondence between the elements of the initial specification and the components of the resultant circuit ensures that the timing constraints under which the evaluation system is designed are respected.