Time Delay Evaluation in Printed Circuit Boards based on Timed Hard Petri Nets

Abstract

This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (HTPN). The implementation of the delay time evaluation system is done by direct mapping of the HTPN into the reconfigurable hardware architecture (FPGA).