FPGA - based implementation of safe Petri nets models

Abstract

In this paper a hardware implementation method of Safe Petri Nets (SaPN) models is proposed. Mapping of SaPN models into FPGA is based on creating of the connections between selected functional elements places P and transitions T according to the incidence matrix. The method allows the implementation of SaPN models of any complexity by reason of flexible architecture of functional elements. Proposed method makes possible the economical and structured FPGA implementation according to AHDL description of processing elements.