Bist logic design for a reduced model of 3–coupling faults in random–access memories

Abstract

A logic design for a built-in self-testing implementation of a march test able to cover a reduced model of 3–coupling faults in n 1 random–access memories (RAMs) is discussed. The logic design is focused on the march test MT-R3CF with 30n operations given by Caşcaval, Bennett, and Huţanu in [1]. To reduce the length of the test, only the coupling faults between physically adjacent memory cells have been considered. To compare marh test MT-R3CF with other published tests, simulation results are also presented in this paper.