A new method of analysis and synthesis of asynchronous sequential circuits

Abstract

In present paper, I propose a new method for analysis and synthesis of an asynchronous sequential system. The main idea consist on building a CK drive in signal, using the transition system function graph. It contains a clock signal who will drive on the states of the sequential system. To control sequential system, it is used a clock signal who contain a set of Master – Slave D latches circuits, logic gates. It was built from the sequential system transition matrix. All the system components are asynchronous, it has no clock signal. For system transitions control actions, it use a built in local clock signal who will drive in the digital system. Using the system fluence graph and fluence table will be build an asynchronous clock signal. It is implemented using logic gates like AND, OR, XOR. Using this method, the asynchronous sequential system can be easy implemented, and it works free of logic hazards.