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Parity analysis of convergent fan-out signals for the Schneider’s counterexample digital circuit
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| dc.contributor.author | COJOCARU, Ion | |
| dc.contributor.author | ŞERBANAŢI, Luca | |
| dc.contributor.author | PĂVĂLOIU, Bujor | |
| dc.contributor.author | RADOVICI, Alexandru | |
| dc.contributor.author | VASILOŢEANU, Andrei | |
| dc.date.accessioned | 2024-01-11T08:37:32Z | |
| dc.date.available | 2024-01-11T08:37:32Z | |
| dc.date.issued | 2009 | |
| dc.identifier.citation | COJOCARU, Ion et al. Parity analysis of convergent fan-out signals for the Schneider’s counterexample digital circuit. In: Microelectronics and Computer Science: proc. 6th International Conference, 1-3 Oct. 2009, Chişinău, Republica Moldova, vol. 1, 2009, pp. 235-238. ISBN 978-9975-45-045-4. ISBN 978-9975-45-122-2 (vol. 1). | en_US |
| dc.identifier.isbn | 978-9975-45-045-4 | |
| dc.identifier.isbn | 978-9975-45-122-2 | |
| dc.identifier.uri | http://repository.utm.md/handle/5014/25778 | |
| dc.description.abstract | The digital circuit, DC, of the counterexample Schneider was used as a logic structure to which it was demonstrated the insufficiently of the sensitization method for one way (DALG-I), for discovering the error 6≡0 and the argument for elaborating DALG-II. In it’s proven that the efficiency of DALG-II was demonstrated for a possible specific error. The results of the testability estimation for this circuit come with a doubt for the correctness of the structure and for the efficiency DALG-II for detecting 6≡1. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Technical University of Moldova | en_US |
| dc.relation.ispartof | Proceeding of the 6th International Conference on "Microelectronics and Computer Science", oct.1-3, 2009, Chişinău, Moldova | |
| dc.rights | Attribution-NonCommercial-NoDerivs 3.0 United States | * |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ | * |
| dc.subject | parity analysis | en_US |
| dc.subject | digital circuits | en_US |
| dc.subject | counterexample Schneider | en_US |
| dc.title | Parity analysis of convergent fan-out signals for the Schneider’s counterexample digital circuit | en_US |
| dc.type | Article | en_US |
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